kopia lustrzana https://github.com/skuep/AIOC
Made Virtual COS/PTT configurable via new configuration interface
rodzic
af0ddf9714
commit
c0fbd8c746
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@ -4,13 +4,43 @@
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#include <stdint.h>
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#include "stm32f3xx_hal.h"
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#include "usb_hid.h"
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#include "settings.h"
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static inline void COS_SetState(uint8_t state)
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{
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LED_SET(0, state & 0x01 ? 1 : 0);
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USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_VOLDN : 0x00);
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USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_DCD : 0x00);
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if (settingsRegMap[SETTINGS_REG_CM108_IOMUX0] & SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK) {
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USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_VOLUP : 0x00);
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}
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if (settingsRegMap[SETTINGS_REG_CM108_IOMUX1] & SETTINGS_REG_CM108_IOMUX1_BTN2SRC_VCOS_MASK) {
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USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_VOLDN : 0x00);
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}
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if (settingsRegMap[SETTINGS_REG_CM108_IOMUX2] & SETTINGS_REG_CM108_IOMUX2_BTN3SRC_VCOS_MASK) {
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USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_PLAYMUTE : 0x00);
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}
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if (settingsRegMap[SETTINGS_REG_CM108_IOMUX3] & SETTINGS_REG_CM108_IOMUX3_BTN4SRC_VCOS_MASK) {
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USB_HIDSendButtonState(state & 0x01 ? USB_HID_BUTTON_RECMUTE : 0x00);
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}
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if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX0] & SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK) {
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USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_DCD : 0x00);
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}
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if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX1] & SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_VCOS_MASK) {
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USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_DSR : 0x00);
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}
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if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX2] & SETTINGS_REG_SERIAL_IOMUX2_RISRC_VCOS_MASK) {
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USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_RI : 0x00);
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}
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if (settingsRegMap[SETTINGS_REG_SERIAL_IOMUX3] & SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_VCOS_MASK) {
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USB_SerialSendLineState(state & 0x01 ? USB_SERIAL_LINESTATE_BREAK : 0x00);
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}
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}
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#endif /* COS_H_ */
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@ -16,6 +16,8 @@
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static inline void PTT_Control(uint8_t pttMask)
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{
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/* TODO: This way, both PTTs can only be asserted/deasserted simultaneously.
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* Maybe better for future applications to have PTT1 and PTT2 controlled separately. */
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__disable_irq();
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if (pttMask & PTT_MASK_PTT1) {
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@ -44,6 +44,7 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALRTS_MASK 0x00000200UL
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#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALDTRNRTS_MASK 0x00000400UL
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#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALNDTRRTS_MASK 0x00000800UL
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#define SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_VPTT_MASK 0x00001000UL
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/* AIOC IOMUX1 register */
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#define SETTINGS_REG_AIOC_IOMUX1 0x25
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@ -61,7 +62,7 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_SERIALRTS_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALRTS_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_SERIALDTRNRTS_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALDTRNRTS_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_SERIALNDTRRTS_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_SERIALNDTRRTS_MASK
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#define SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_VPTT_MASK SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_VPTT_MASK
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/* CM108 IOMUX0 register */
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#define SETTINGS_REG_CM108_IOMUX0 0x44
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@ -112,17 +113,17 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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#define SETTINGS_REG_CM108_IOMUX3_BTN4SRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK
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/* Serial (CDC) Control register */
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#define SETTINGS_REG_SERIAL_CTRL 0x50
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#define SETTINGS_REG_SERIAL_CTRL 0x60
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#define SETTINGS_REG_SERIAL_CTRL_DEFAULT (SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_DFLT | SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_DFLT)
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/* TXFRCPTT: Forces PTT signal(s) to zero when transmitting serial data to radio if enabled */
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_DFLT (SETTINGS_REG_SERIAL_CTRL_FORCEPTT_PTT1)
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_DFLT (SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_PTT1_MASK)
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_OFFS 8
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_MASK 0x00000F00UL
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_NONE_MASK 0x00000000UL
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_PTT1_MASK 0x00000100UL
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#define SETTINGS_REG_SERIAL_CTRL_TXFRCPTT_PTT2_MASK 0x00000200UL
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/* RXIGNPTT: Ignores reception of data from radio when PTT signal(s) asserted if enabled */
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_DFLT (SETTINGS_REG_SERIAL_CTRL_IGNPTT_PTT1)
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_DFLT (SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_PTT1_MASK)
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_OFFS 16
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_MASK 0x000F0000UL
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_NONE_MASK 0x00000000UL
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@ -130,7 +131,7 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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#define SETTINGS_REG_SERIAL_CTRL_RXIGNPTT_PTT2_MASK 0x00020000UL
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/* Serial (CDC) IOMUX0 register */
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#define SETTINGS_REG_SERIAL_IOMUX0 0x54
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#define SETTINGS_REG_SERIAL_IOMUX0 0x64
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#define SETTINGS_REG_SERIAL_IOMUX0_DEFAULT (SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_DFLT)
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/* DCDSRC: DCD (Data Carrier Detect) signal source */
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_DFLT (SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK)
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@ -142,7 +143,7 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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#define SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK SETTINGS_REG_CM108_IOMUX0_BTN1SRC_VCOS_MASK
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/* Serial (CDC) IOMUX1 register */
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#define SETTINGS_REG_SERIAL_IOMUX1 0x55
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#define SETTINGS_REG_SERIAL_IOMUX1 0x65
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#define SETTINGS_REG_SERIAL_IOMUX1_DEFAULT (SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_DFLT)
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/* DSRSRC: DSR (Data Set Ready) signal source */
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_DFLT (SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_NONE_MASK)
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@ -154,7 +155,7 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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#define SETTINGS_REG_SERIAL_IOMUX1_DSRSRC_VCOS_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK
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/* Serial (CDC) IOMUX2 register */
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#define SETTINGS_REG_SERIAL_IOMUX2 0x56
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#define SETTINGS_REG_SERIAL_IOMUX2 0x66
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#define SETTINGS_REG_SERIAL_IOMUX2_DEFAULT (SETTINGS_REG_SERIAL_IOMUX2_RISRC_DFLT)
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/* RISRC: RI (Ring Indicator) signal source */
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_DFLT (SETTINGS_REG_SERIAL_IOMUX2_RISRC_NONE_MASK)
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@ -166,7 +167,7 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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#define SETTINGS_REG_SERIAL_IOMUX2_RISRC_VCOS_MASK SETTINGS_REG_SERIAL_IOMUX0_DCDSRC_VCOS_MASK
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/* Serial (CDC) IOMUX3 register */
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#define SETTINGS_REG_SERIAL_IOMUX3 0x57
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#define SETTINGS_REG_SERIAL_IOMUX3 0x67
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#define SETTINGS_REG_SERIAL_IOMUX3_DEFAULT (SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_DFLT)
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/* BRKSRC: BREAK (Break) signal source */
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#define SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_DFLT (SETTINGS_REG_SERIAL_IOMUX3_BRKSRC_NONE_MASK)
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@ -197,7 +198,7 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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#define SETTINGS_REG_VCOS_LVLCTRL 0x92
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#define SETTINGS_REG_VCOS_LVLCTRL_DEFAULT (SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_DFLT)
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/* THRSHLD: Virtual COS threshold level */
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#define SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_DFLT ((uint32_t) 16 << SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_OFFS)
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#define SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_DFLT ((uint32_t) 256 << SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_OFFS)
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#define SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_OFFS 0
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#define SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_MASK 0x0000FFFFUL
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@ -18,11 +18,6 @@
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/* We try to stay on this target with the buffer level */
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#define SPEAKER_BUFFERLVL_TARGET (5 * CFG_TUD_AUDIO_EP_SZ_OUT) /* Keep our buffer at 5 frames, i.e. 5ms at full-speed USB and maximum sample rate */
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#define PTT_THRESHOLD 16
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#define PTT_TIMEOUT 10000 /* us */
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#define COS_THRESHOLD (16 << 4)
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#define COS_TIMEOUT 10000 /* us */
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typedef enum {
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SAMPLERATE_48000, /* The high-quality default */
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@ -653,7 +648,9 @@ void ADC1_2_IRQHandler (void)
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int16_t sample = ((int32_t) ADC2->DR - 32768) & 0xFFFFU;
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/* Automatic COS */
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if (!microphoneMute[1] && ( (sample > COS_THRESHOLD) || (sample < -COS_THRESHOLD) )) {
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uint16_t cosThreshold = (settingsRegMap[SETTINGS_REG_VCOS_LVLCTRL] & SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_MASK) >> SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_OFFS;
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if (!microphoneMute[1] && ( (sample > cosThreshold) || (sample < -cosThreshold) )) {
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/* Reset timeout and make sure timer is enabled */
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TIM17->EGR = TIM_EGR_UG; /* Generate an update event in the timer */
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}
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@ -679,7 +676,9 @@ void TIM6_DAC_IRQHandler(void)
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tud_audio_read(&sample, sizeof(sample));
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/* Automatic PTT */
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if (!speakerMute[1] && ( (sample > PTT_THRESHOLD) || (sample < -PTT_THRESHOLD) )) {
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uint16_t pttThreshold = (settingsRegMap[SETTINGS_REG_VPTT_LVLCTRL] & SETTINGS_REG_VPTT_LVLCTRL_THRSHLD_MASK) >> SETTINGS_REG_VPTT_LVLCTRL_THRSHLD_OFFS;
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if (!speakerMute[1] && ( (sample > pttThreshold) || (sample < -pttThreshold) )) {
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/* Reset timeout and make sure timer is enabled */
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TIM16->EGR = TIM_EGR_UG; /* Generate an update event in the timer */
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}
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@ -706,7 +705,11 @@ void TIM16_IRQHandler(void)
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if (!(cr & TIM_CR1_CEN)) {
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/* If timer was not enabled previously, enable timer and assert PTT */
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TIM16->CR1 = cr | TIM_CR1_CEN;
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PTT_Control(PTT_MASK_PTT1);
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uint8_t pttMask = PTT_MASK_NONE;
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pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX0] & SETTINGS_REG_AIOC_IOMUX0_PTT1SRC_VPTT_MASK ? PTT_MASK_PTT1 : 0;
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pttMask |= settingsRegMap[SETTINGS_REG_AIOC_IOMUX1] & SETTINGS_REG_AIOC_IOMUX1_PTT2SRC_VPTT_MASK ? PTT_MASK_PTT2 : 0;
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PTT_Control(pttMask);
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}
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} else if (flags & TIM_SR_CC1IF) {
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/* The idle timeout (without any action on the DAC) was reached. Disable timer and deassert PTT */
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@ -875,6 +878,8 @@ static void DAC_Init(void)
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static void Timeout_Timers_Init()
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{
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uint32_t timerFreq = (HAL_RCC_GetHCLKFreq() == HAL_RCC_GetPCLK2Freq()) ? HAL_RCC_GetPCLK2Freq() : 2 * HAL_RCC_GetPCLK2Freq();
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uint32_t pttTimeout = (settingsRegMap[SETTINGS_REG_VPTT_TIMCTRL] & SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_MASK) >> SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS;
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uint32_t cosTimeout = (settingsRegMap[SETTINGS_REG_VCOS_TIMCTRL] & SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_MASK) >> SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS;
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__HAL_RCC_TIM16_CLK_ENABLE();
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__HAL_RCC_TIM17_CLK_ENABLE();
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@ -882,12 +887,12 @@ static void Timeout_Timers_Init()
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/* TIM16 and TIM17 are timeout-counters for PTT and COS */
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TIM16->CR1 = TIM_CLOCKDIVISION_DIV1 | TIM_COUNTERMODE_UP;
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TIM16->PSC = timerFreq / 1000000 - 1; /* Microseconds counter */
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TIM16->CCR1 = PTT_TIMEOUT - 1;
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TIM16->CCR1 = pttTimeout - 1;
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TIM16->DIER = TIM_DIER_UIE | TIM_DIER_CC1IE;
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TIM17->CR1 = TIM_CLOCKDIVISION_DIV1 | TIM_COUNTERMODE_UP;
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TIM17->PSC = timerFreq / 1000000 - 1; /* Microseconds counter */
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TIM17->CCR1 = COS_TIMEOUT - 1;
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TIM17->CCR1 = cosTimeout - 1;
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TIM17->DIER = TIM_DIER_UIE | TIM_DIER_CC1IE;
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NVIC_SetPriority(TIM16_IRQn, AIOC_IRQ_PRIO_AUDIO);
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@ -51,8 +51,8 @@ tusb_desc_device_t desc_device = {
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// Application return pointer to descriptor
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uint8_t const* tud_descriptor_device_cb(void) {
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/* Get up-to-date USB settings */
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desc_device.idVendor = (settingsRegMap[SETTINGS_REG_USBID] >> SETTINGS_REG_USBID_VID_OFFS) & SETTINGS_REG_USBID_VID_MASK;
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desc_device.idProduct = (settingsRegMap[SETTINGS_REG_USBID] >> SETTINGS_REG_USBID_PID_OFFS) & SETTINGS_REG_USBID_PID_MASK;
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desc_device.idVendor = (settingsRegMap[SETTINGS_REG_USBID] & SETTINGS_REG_USBID_VID_MASK) >> SETTINGS_REG_USBID_VID_OFFS;
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desc_device.idProduct = (settingsRegMap[SETTINGS_REG_USBID] & SETTINGS_REG_USBID_PID_MASK) >> SETTINGS_REG_USBID_PID_OFFS;
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return (uint8_t const*) &desc_device;
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}
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