kopia lustrzana https://github.com/skuep/AIOC
Implemented OPAMP functionality for v1.2 hardware
Simon Kueppers
Simon Küppers
rodzic
b61957be94
commit
868ac9323b
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@ -54,7 +54,7 @@
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/* #define HAL_I2S_MODULE_ENABLED */
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/* #define HAL_IRDA_MODULE_ENABLED */
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#define HAL_IWDG_MODULE_ENABLED
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/* #define HAL_OPAMP_MODULE_ENABLED */
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#define HAL_OPAMP_MODULE_ENABLED
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/* #define HAL_PCD_MODULE_ENABLED */
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#define HAL_PWR_MODULE_ENABLED
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#define HAL_RCC_MODULE_ENABLED
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@ -76,8 +76,11 @@ static void Timer_ADC_Init(void);
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static void Timer_DAC_Init(void);
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static void ADC_Init(void);
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static void DAC_Init(void);
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static void RX_Config(usb_audio_rxgain_t rxGain);
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static void TX_Config(usb_audio_txboost_t txBoost);
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static void Timeout_Timers_Init(void);
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//--------------------------------------------------------------------+
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// Application Callback API Implementations
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//--------------------------------------------------------------------+
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@ -516,6 +519,7 @@ bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, u
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if (microphoneState == STATE_START) {
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/* Start ADC sampling as soon as device stacks starts loading data (will be a ZLP for first frame) */
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RX_Config(USB_AUDIO_RXGAIN_1X);
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NVIC_EnableIRQ(ADC1_2_IRQn);
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microphoneState = STATE_RUN;
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@ -539,8 +543,9 @@ bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, u
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if (speakerState == STATE_START) {
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if (count >= SPEAKER_BUFFERLVL_TARGET) {
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/* Wait until whe are at buffer target fill level, then start DAC output */
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/* Wait until we are at buffer target fill level, then start DAC output */
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speakerState = STATE_RUN;
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TX_Config(USB_AUDIO_TXBOOST_OFF);
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NVIC_EnableIRQ(TIM6_DAC1_IRQn);
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/* Update debug register */
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@ -718,10 +723,19 @@ TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t
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void ADC1_2_IRQHandler (void)
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{
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if (ADC2->ISR & ADC_ISR_EOS) {
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ADC2->ISR = ADC_ISR_EOS;
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if ( (ADC1->ISR & ADC_ISR_EOS) || (ADC2->ISR & ADC_ISR_EOS) ) {
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int16_t sample = 0;
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/* Get ADC sample */
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int16_t sample = ((int32_t) ADC2->DR - 32768) & 0xFFFFU;
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if (ADC1->ISR & ADC_ISR_EOS) {
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ADC1->ISR = ADC_ISR_EOS;
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sample = ((int32_t) ADC1->DR - 32768) & 0xFFFFU;
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}
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if (ADC2->ISR & ADC_ISR_EOS) {
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ADC2->ISR = ADC_ISR_EOS;
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sample = ((int32_t) ADC2->DR - 32768) & 0xFFFFU;
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}
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/* Automatic COS */
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uint16_t cosThreshold = (settingsRegMap[SETTINGS_REG_VCOS_LVLCTRL] & SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_MASK) >> SETTINGS_REG_VCOS_LVLCTRL_THRSHLD_OFFS;
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@ -844,6 +858,7 @@ void TIM17_IRQHandler(void)
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static void GPIO_Init(void)
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{
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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GPIO_InitTypeDef ADCInGpio;
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@ -854,6 +869,22 @@ static void GPIO_Init(void)
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ADCInGpio.Alternate = 0;
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HAL_GPIO_Init(GPIOB, &ADCInGpio);
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GPIO_InitTypeDef OPAMP1InGpio;
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OPAMP1InGpio.Pin = GPIO_PIN_5;
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OPAMP1InGpio.Mode = GPIO_MODE_ANALOG;
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OPAMP1InGpio.Pull = GPIO_NOPULL;
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OPAMP1InGpio.Speed = GPIO_SPEED_FREQ_LOW;
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OPAMP1InGpio.Alternate = 0;
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HAL_GPIO_Init(GPIOA, &OPAMP1InGpio);
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GPIO_InitTypeDef OPAMP2OutGpio;
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OPAMP2OutGpio.Pin = GPIO_PIN_6;
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OPAMP2OutGpio.Mode = GPIO_MODE_ANALOG;
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OPAMP2OutGpio.Pull = GPIO_NOPULL;
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OPAMP2OutGpio.Speed = GPIO_SPEED_FREQ_LOW;
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OPAMP2OutGpio.Alternate = 0;
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HAL_GPIO_Init(GPIOA, &OPAMP2OutGpio);
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GPIO_InitTypeDef SamplerateGpio;
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SamplerateGpio.Pin = GPIO_PIN_0;
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SamplerateGpio.Mode = GPIO_MODE_AF_PP;
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@ -869,6 +900,14 @@ static void GPIO_Init(void)
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DACOutGpio.Speed = GPIO_SPEED_FREQ_LOW;
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DACOutGpio.Alternate = 0;
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HAL_GPIO_Init(GPIOA, &DACOutGpio);
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GPIO_InitTypeDef DACAttenGpio;
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DACAttenGpio.Pin = GPIO_PIN_3;
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DACAttenGpio.Mode = GPIO_MODE_OUTPUT_OD;
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DACAttenGpio.Pull = GPIO_NOPULL;
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DACAttenGpio.Speed = GPIO_SPEED_FREQ_LOW;
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DACAttenGpio.Alternate = 0;
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HAL_GPIO_Init(GPIOA, &DACAttenGpio);
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}
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static void Timer_ADC_Init(void)
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@ -926,9 +965,13 @@ static void Timer_DAC_Init(void)
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static void ADC_Init(void)
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{
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/* We use two ADCs. ADC1 is used, when OPAMP(PGA) is used. Otherwise ADC2 with direct hardware connection is used */
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__HAL_RCC_ADC1_CLK_ENABLE();
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__HAL_RCC_ADC2_CLK_ENABLE();
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ADC1->CR = 0x00 << ADC_CR_ADVREGEN_Pos;
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ADC2->CR = 0x00 << ADC_CR_ADVREGEN_Pos;
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ADC1->CR = 0x01 << ADC_CR_ADVREGEN_Pos;
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ADC2->CR = 0x01 << ADC_CR_ADVREGEN_Pos;
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for (uint32_t i=0; i<200; i++) {
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@ -938,32 +981,35 @@ static void ADC_Init(void)
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/* Select AHB clock */
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ADC12_COMMON->CCR = (0x1 << ADC12_CCR_CKMODE_Pos) | (0x00 << ADC12_CCR_MULTI_Pos);
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ADC1->CR |= ADC_CR_ADCAL;
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ADC2->CR |= ADC_CR_ADCAL;
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while (ADC2->CR & ADC_CR_ADCAL)
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while ( (ADC1->CR & ADC_CR_ADCAL) || (ADC2->CR & ADC_CR_ADCAL) )
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;
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ADC1->CR |= ADC_CR_ADEN;
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ADC2->CR |= ADC_CR_ADEN;
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/* Wait for ADC to be ready */
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while (!(ADC2->ISR & ADC_ISR_ADRDY))
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while (!(ADC1->ISR & ADC_ISR_ADRDY) || !(ADC2->ISR & ADC_ISR_ADRDY) )
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;
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/* External Trigger on TIM3_TRGO, left aligned data with 12 bit resolution */
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ADC1->CFGR = (0x01 << ADC_CFGR_EXTEN_Pos) | (0x04 << ADC_CFGR_EXTSEL_Pos) | (ADC_CFGR_ALIGN) | (0x00 << ADC_CFGR_RES_Pos);
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ADC2->CFGR = (0x01 << ADC_CFGR_EXTEN_Pos) | (0x04 << ADC_CFGR_EXTSEL_Pos) | (ADC_CFGR_ALIGN) | (0x00 << ADC_CFGR_RES_Pos);
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/* Maximum sample time of 601.5 cycles for channel 12. */
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/* Maximum sample time of 601.5 cycles for channel 3/channel 12. */
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ADC1->SMPR1 = 0x7 << ADC_SMPR1_SMP3_Pos;
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ADC2->SMPR2 = 0x7 << ADC_SMPR2_SMP12_Pos;
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/* Sample only channel 12 in a regular sequence */
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/* Sample only channel 3/channel 12 in a regular sequence */
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ADC1->SQR1 = ( 3 << ADC_SQR1_SQ1_Pos) | (0 << ADC_SQR1_L_Pos);
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ADC2->SQR1 = (12 << ADC_SQR1_SQ1_Pos) | (0 << ADC_SQR1_L_Pos);
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/* Enable Interrupt Request */
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ADC1->IER = ADC_IER_EOSIE;
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ADC2->IER = ADC_IER_EOSIE;
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/* Start ADC */
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ADC2->CR |= ADC_CR_ADSTART;
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NVIC_SetPriority(ADC1_2_IRQn, AIOC_IRQ_PRIO_AUDIO);
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}
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@ -973,9 +1019,79 @@ static void DAC_Init(void)
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/* Select TIM6 TRGO as trigger and enable DAC */
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DAC->CR = (0x0 << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1;
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/* Output VDD/2 */
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DAC1->DHR12L1 = 32768;
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}
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static void Timeout_Timers_Init()
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static void RX_Config(usb_audio_rxgain_t rxGain)
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{
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/* Disable OPAMPs */
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OPAMP1->CSR = 0x00;
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OPAMP2->CSR = 0x00;
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if (rxGain == USB_AUDIO_RXGAIN_1X) {
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/* Legacy mode that is compatible with pre-v1.2 hardware */
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OPAMP2->CSR = OPAMP_FOLLOWER_MODE | OPAMP_VREF_50VDDA | OPAMP_CSR_FORCEVP | OPAMP2_CSR_OPAMP2EN; /* 50% VDD for bias */
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/* Start ADC2 with direct hardware ADC input (no PGA in between) */
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if (ADC1->CR & ADC_CR_ADSTART) ADC1->CR |= ADC_CR_ADSTP;
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if (!(ADC2->CR & ADC_CR_ADSTART)) ADC2->CR |= ADC_CR_ADSTART;
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} else {
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/* Initialize OPAMPs so that OPAMP1 is a PGA (non inverting) and OPAMP2 produces the correct DC-bias voltage according to OPAMP1 gain. */
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static const uint32_t pgaConfig[] = {
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[USB_AUDIO_RXGAIN_2X] = OPAMP_PGA_MODE | OPAMP_PGA_GAIN_2, /* ADCin: 0.825V +/- 0.825V */
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[USB_AUDIO_RXGAIN_4X] = OPAMP_PGA_MODE | OPAMP_PGA_GAIN_4, /* ADCin: 0.4125V +/- 0.4125V */
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[USB_AUDIO_RXGAIN_8X] = OPAMP_PGA_MODE | OPAMP_PGA_GAIN_8, /* ADCin: 0.20625V +/- 0.20625V */
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[USB_AUDIO_RXGAIN_16X] = OPAMP_PGA_MODE | OPAMP_PGA_GAIN_16 /* ADCin: 0.103125V +/- 0.103125V */
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};
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static const uint32_t biasConfig[] = {
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[USB_AUDIO_RXGAIN_2X] = OPAMP_PGA_MODE | OPAMP_PGA_GAIN_8, /* 3.3V * 3.3% * 8 = 0.8712V */
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[USB_AUDIO_RXGAIN_4X] = OPAMP_PGA_MODE | OPAMP_PGA_GAIN_4, /* 3.3V * 3.3% * 4 = 0.4356V */
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[USB_AUDIO_RXGAIN_8X] = OPAMP_PGA_MODE | OPAMP_PGA_GAIN_2, /* 3.3V * 3.3% * 2 = 0.2178V */
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[USB_AUDIO_RXGAIN_16X] = OPAMP_FOLLOWER_MODE /* 3.3V * 3.3% * 1 = 0.1089V */
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};
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/* Set up OPAMP1 PGA */
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OPAMP1->CSR = pgaConfig[rxGain] | OPAMP_NONINVERTINGINPUT_IO3 | OPAMP1_CSR_OPAMP1EN;
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/* Add a trimming offset adjustment to get closer to the required bias voltage reference of 1.65V/16 = 103mV.
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* Default setting is 3.3V * 3.3% = 109mV.
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* These return the factory trim values, because the CSR register (and thus the USERTRIM bit) is 0 */
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uint32_t trimmingOffsetP2 = (OPAMP2->CSR & OPAMP2_CSR_TRIMOFFSETP_Msk) >> OPAMP2_CSR_TRIMOFFSETP_Pos;
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uint32_t trimmingOffsetN2 = (OPAMP2->CSR & OPAMP2_CSR_TRIMOFFSETN_Msk) >> OPAMP2_CSR_TRIMOFFSETN_Pos;
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int8_t trimAdjust = 7; /* Found empirically. It looks like 1 step amounts to roughly 1mV input offset */
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/* Observe the register limits, do saturated arithmetic */
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trimmingOffsetP2 = (((int32_t) trimmingOffsetP2 + trimAdjust) <= 0x1F) ? trimmingOffsetP2 + trimAdjust : 0x1F;
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trimmingOffsetN2 = (((int32_t) trimmingOffsetN2 - trimAdjust) >= 0x00) ? trimmingOffsetN2 - trimAdjust : 0x00;
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/* Set up OPAMP2 bias voltage generation, disable the factory trimming */
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OPAMP2->CSR = biasConfig[rxGain] | OPAMP_VREF_3VDDA | OPAMP_CSR_FORCEVP | OPAMP2_CSR_OPAMP2EN | OPAMP_TRIMMING_USER;
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/* Load trimming values */
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OPAMP2->CSR |= (OPAMP2->CSR & ~(OPAMP2_CSR_TRIMOFFSETP_Msk | OPAMP2_CSR_TRIMOFFSETN_Msk)) |
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((trimmingOffsetP2 << OPAMP2_CSR_TRIMOFFSETP_Pos) & OPAMP2_CSR_TRIMOFFSETP_Msk) |
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((trimmingOffsetN2 << OPAMP2_CSR_TRIMOFFSETN_Pos) & OPAMP2_CSR_TRIMOFFSETN_Msk);
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/* Start ADC1 using PGA output as ADC input */
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if (ADC2->CR & ADC_CR_ADSTART) ADC2->CR |= ADC_CR_ADSTP;
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if (!(ADC1->CR & ADC_CR_ADSTART)) ADC1->CR |= ADC_CR_ADSTART;
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}
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}
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static void TX_Config(usb_audio_txboost_t txBoost)
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{
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/* Set PINA3 (ATTEN Hi-Z) in TX Boost mode, reset PINA3 (pull ATTEN low) in normal mode */
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if (txBoost == USB_AUDIO_TXBOOST_ON) {
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GPIOA->BSRR = GPIO_BSRR_BS_3;
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} else {
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GPIOA->BRR = GPIO_BRR_BR_3;
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}
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}
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static void Timeout_Timers_Init(void)
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{
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uint32_t timerFreq = (HAL_RCC_GetHCLKFreq() == HAL_RCC_GetPCLK2Freq()) ? HAL_RCC_GetPCLK2Freq() : 2 * HAL_RCC_GetPCLK2Freq();
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uint32_t pttTimeout = (settingsRegMap[SETTINGS_REG_VPTT_TIMCTRL] & SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_MASK) >> SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS;
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@ -3,6 +3,19 @@
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#include <stdint.h>
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typedef enum {
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USB_AUDIO_RXGAIN_1X,
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USB_AUDIO_RXGAIN_2X,
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USB_AUDIO_RXGAIN_4X,
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USB_AUDIO_RXGAIN_8X,
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USB_AUDIO_RXGAIN_16X,
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} usb_audio_rxgain_t;
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typedef enum {
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USB_AUDIO_TXBOOST_OFF,
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USB_AUDIO_TXBOOST_ON
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} usb_audio_txboost_t;
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typedef struct {
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uint16_t bufLevelMin;
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uint16_t bufLevelMax;
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