kopia lustrzana https://github.com/skuep/AIOC
Added various read-only debug registers to register map
Simon Kueppers
rodzic
e853047a2c
commit
2fd3f70917
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@ -15,7 +15,7 @@ void Settings_Init()
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uint8_t Settings_RegWrite(uint8_t address, const uint8_t * buffer, uint8_t bufsize)
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uint8_t Settings_RegWrite(uint8_t address, const uint8_t * buffer, uint8_t bufsize)
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{
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{
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if (address < SETTINGS_REGMAP_SIZE) {
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if (address < SETTINGS_REGMAP_READONLYADDR) {
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assert(bufsize == sizeof(uint32_t));
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assert(bufsize == sizeof(uint32_t));
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uint32_t data = ( (((uint32_t) buffer[0]) << 0) |
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uint32_t data = ( (((uint32_t) buffer[0]) << 0) |
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@ -23,7 +23,9 @@ uint8_t Settings_RegWrite(uint8_t address, const uint8_t * buffer, uint8_t bufsi
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(((uint32_t) buffer[2]) << 16) |
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(((uint32_t) buffer[2]) << 16) |
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(((uint32_t) buffer[3]) << 24) );
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(((uint32_t) buffer[3]) << 24) );
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__disable_irq();
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settingsRegMap[address] = data;
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settingsRegMap[address] = data;
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__enable_irq();
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return bufsize;
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return bufsize;
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}
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}
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@ -36,7 +38,9 @@ uint8_t Settings_RegRead(uint8_t address, uint8_t * buffer, uint8_t bufsize)
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if (address < SETTINGS_REGMAP_SIZE) {
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if (address < SETTINGS_REGMAP_SIZE) {
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assert(bufsize == sizeof(uint32_t));
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assert(bufsize == sizeof(uint32_t));
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__disable_irq();
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uint64_t data = settingsRegMap[address];
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uint64_t data = settingsRegMap[address];
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__enable_irq();
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buffer[0] = (uint8_t) (data >> 0);
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buffer[0] = (uint8_t) (data >> 0);
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buffer[1] = (uint8_t) (data >> 8);
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buffer[1] = (uint8_t) (data >> 8);
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@ -52,9 +56,12 @@ void Settings_Store(void)
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HAL_FLASH_Unlock();
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HAL_FLASH_Unlock();
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uint32_t pageError = 0;
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uint32_t pageError = 0;
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extern uint32_t * _eeprom;
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uint32_t pageAddress = (uint32_t) &_eeprom;
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FLASH_EraseInitTypeDef eraseInitStruct = {
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FLASH_EraseInitTypeDef eraseInitStruct = {
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.TypeErase = FLASH_TYPEERASE_PAGES,
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.TypeErase = FLASH_TYPEERASE_PAGES,
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.PageAddress = SETTINGS_FLASH_ADDRESS,
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.PageAddress = pageAddress,
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.NbPages = (SETTINGS_REGMAP_SIZE * sizeof(uint32_t) + FLASH_PAGE_SIZE-1) / FLASH_PAGE_SIZE
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.NbPages = (SETTINGS_REGMAP_SIZE * sizeof(uint32_t) + FLASH_PAGE_SIZE-1) / FLASH_PAGE_SIZE
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};
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};
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@ -64,7 +71,8 @@ void Settings_Store(void)
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return;
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return;
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}
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}
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uint32_t wordAddress = SETTINGS_FLASH_ADDRESS;
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extern uint32_t * _eeprom;
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uint32_t wordAddress = (uint32_t) &_eeprom;
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uint32_t wordCount = SETTINGS_REGMAP_SIZE;
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uint32_t wordCount = SETTINGS_REGMAP_SIZE;
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uint32_t * wordPtr = settingsRegMap;
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uint32_t * wordPtr = settingsRegMap;
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@ -134,5 +142,25 @@ void Settings_Default(void)
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settingsRegMap[SETTINGS_REG_VCOS_LVLCTRL] = SETTINGS_REG_VCOS_LVLCTRL_DEFAULT;
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settingsRegMap[SETTINGS_REG_VCOS_LVLCTRL] = SETTINGS_REG_VCOS_LVLCTRL_DEFAULT;
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settingsRegMap[SETTINGS_REG_VCOS_TIMCTRL] = SETTINGS_REG_VCOS_TIMCTRL_DEFAULT;
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settingsRegMap[SETTINGS_REG_VCOS_TIMCTRL] = SETTINGS_REG_VCOS_TIMCTRL_DEFAULT;
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/* AIOC Debug registers */
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settingsRegMap[SETTINGS_REG_DBGAIOC0] = SETTINGS_REG_DBGAIOC0_DEFAULT;
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/* Audio Debug registers */
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settingsRegMap[SETTINGS_REG_DBGAUDIO0] = SETTINGS_REG_DBGAUDIO0_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO1] = SETTINGS_REG_DBGAUDIO1_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO2] = SETTINGS_REG_DBGAUDIO2_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO3] = SETTINGS_REG_DBGAUDIO3_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO4] = SETTINGS_REG_DBGAUDIO4_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO5] = SETTINGS_REG_DBGAUDIO5_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO6] = SETTINGS_REG_DBGAUDIO6_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO7] = SETTINGS_REG_DBGAUDIO7_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO8] = SETTINGS_REG_DBGAUDIO9_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO9] = SETTINGS_REG_DBGAUDIO10_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO10] = SETTINGS_REG_DBGAUDIO11_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO11] = SETTINGS_REG_DBGAUDIO11_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO12] = SETTINGS_REG_DBGAUDIO12_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO13] = SETTINGS_REG_DBGAUDIO13_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO14] = SETTINGS_REG_DBGAUDIO14_DEFAULT;
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settingsRegMap[SETTINGS_REG_DBGAUDIO15] = SETTINGS_REG_DBGAUDIO15_DEFAULT;
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}
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}
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@ -5,6 +5,7 @@
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#include "usb_descriptors.h"
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#include "usb_descriptors.h"
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#define SETTINGS_REGMAP_SIZE 256
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#define SETTINGS_REGMAP_SIZE 256
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#define SETTINGS_REGMAP_READONLYADDR 0xC0
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extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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@ -188,10 +189,10 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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/* Virtual PTT timing control register */
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/* Virtual PTT timing control register */
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#define SETTINGS_REG_VPTT_TIMCTRL 0x84
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#define SETTINGS_REG_VPTT_TIMCTRL 0x84
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#define SETTINGS_REG_VPTT_TIMCTRL_DEFAULT (SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT)
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#define SETTINGS_REG_VPTT_TIMCTRL_DEFAULT (SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT)
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/* TIMEOUT: Timeout (trailing) time in microseconds */
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/* TIMEOUT: Timeout (trailing) time in milliseconds in 12.4 format */
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT ((uint32_t) 10000 << SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS)
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_DFLT ((uint32_t) (20 << 4) << SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS)
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS 0
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_OFFS 0
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_MASK 0x0000FFFFUL
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#define SETTINGS_REG_VPTT_TIMCTRL_TIMEOUT_MASK 0xFFFFFFFFUL
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/* Virtual COS level control register */
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/* Virtual COS level control register */
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#define SETTINGS_REG_VCOS_LVLCTRL 0x92
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#define SETTINGS_REG_VCOS_LVLCTRL 0x92
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@ -204,11 +205,140 @@ extern uint32_t settingsRegMap[SETTINGS_REGMAP_SIZE];
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/* Virtual COS timing control register */
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/* Virtual COS timing control register */
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#define SETTINGS_REG_VCOS_TIMCTRL 0x94
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#define SETTINGS_REG_VCOS_TIMCTRL 0x94
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#define SETTINGS_REG_VCOS_TIMCTRL_DEFAULT (SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT)
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#define SETTINGS_REG_VCOS_TIMCTRL_DEFAULT (SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT)
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/* TIMEOUT: Timeout (trailing) time in microseconds */
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/* TIMEOUT: Timeout (trailing) time in milliseconds in 12.4 format */
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT ((uint32_t) 10000 << SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS)
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_DFLT ((uint32_t) (200 << 4) << SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS)
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS 0
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_OFFS 0
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_MASK 0x0000FFFFUL
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#define SETTINGS_REG_VCOS_TIMCTRL_TIMEOUT_MASK 0x0000FFFFUL
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/* AIOC debug register 0 */
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#define SETTINGS_REG_DBGAIOC0 0xC0
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#define SETTINGS_REG_DBGAIOC0_DEFAULT 0
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/* Various digital signal states */
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#define SETTINGS_REG_DBGAIOC0_PTT1STATE_MASK 0x00010000UL
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#define SETTINGS_REG_DBGAIOC0_PTT2STATE_MASK 0x00020000UL
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/* UAC audio debug register 0 */
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#define SETTINGS_REG_DBGAUDIO0 0xD0
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#define SETTINGS_REG_DBGAUDIO0_DEFAULT 0
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/* Playback or recording muted (master and first channel) */
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#define SETTINGS_REG_DBGAUDIO0_RECMUTE0_MASK 0x00010000UL
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#define SETTINGS_REG_DBGAUDIO0_RECMUTE1_MASK 0x00020000UL
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#define SETTINGS_REG_DBGAUDIO0_PLAYMUTE0_MASK 0x00100000UL
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#define SETTINGS_REG_DBGAUDIO0_PLAYMUTE1_MASK 0x00200000UL
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/* Virtual PTT and COS states */
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#define SETTINGS_REG_DBGAIOC0_VPTTSTATE_MASK 0x01000000UL
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#define SETTINGS_REG_DBGAIOC0_VCOSSTATE_MASK 0x10000000UL
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/* Playback and recording state */
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#define SETTINGS_REG_DBGAUDIO0_RECSTATE_OFFS 24
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#define SETTINGS_REG_DBGAUDIO0_RECSTATE_MASK 0x0F000000UL
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#define SETTINGS_REG_DBGAUDIO0_RECSTATE_OFF_ENUM 0
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#define SETTINGS_REG_DBGAUDIO0_RECSTATE_START_ENUM 1
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#define SETTINGS_REG_DBGAUDIO0_RECSTATE_RUN_ENUM 2
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#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_OFFS 28
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#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_MASK 0xF0000000UL
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#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_OFF_ENUM 0
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#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_START_ENUM 1
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#define SETTINGS_REG_DBGAUDIO0_PLAYSTATE_RUN_ENUM 2
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/* Audio debug register 1 */
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#define SETTINGS_REG_DBGAUDIO1 0xD1
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#define SETTINGS_REG_DBGAUDIO1_DEFAULT 0
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/* Audio debug register 2 */
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#define SETTINGS_REG_DBGAUDIO2 0xD2
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#define SETTINGS_REG_DBGAUDIO2_DEFAULT 0
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/* Recording samplerate */
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#define SETTINGS_REG_DBGAUDIO2_RECRATE_OFFS 0
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#define SETTINGS_REG_DBGAUDIO2_RECRATE_MASK 0xFFFFFFFFUL
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/* Audio debug register 3 */
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#define SETTINGS_REG_DBGAUDIO3 0xD3
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#define SETTINGS_REG_DBGAUDIO3_DEFAULT 0
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/* Recording volume (master and first channel) */
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#define SETTINGS_REG_DBGAUDIO3_RECVOL0_OFFS 0
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#define SETTINGS_REG_DBGAUDIO3_RECVOL0_MASK 0x0000FFFFUL
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#define SETTINGS_REG_DBGAUDIO3_RECVOL1_OFFS 16
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#define SETTINGS_REG_DBGAUDIO3_RECVOL1_MASK 0xFFFF0000UL
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/* TODO: D4, D5, D6 -> Recording buffer levels (avg/min/max) */
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/* Audio debug register 4 */
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#define SETTINGS_REG_DBGAUDIO4 0xD4
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#define SETTINGS_REG_DBGAUDIO4_DEFAULT 0
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/* Audio debug register 5 */
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#define SETTINGS_REG_DBGAUDIO5 0xD5
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#define SETTINGS_REG_DBGAUDIO5_DEFAULT 0
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/* Audio debug register 6 */
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#define SETTINGS_REG_DBGAUDIO6 0xD6
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#define SETTINGS_REG_DBGAUDIO6_DEFAULT 0
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/* Audio debug register 7 */
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#define SETTINGS_REG_DBGAUDIO7 0xD7
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#define SETTINGS_REG_DBGAUDIO7_DEFAULT 0
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/* Audio debug register 8 */
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#define SETTINGS_REG_DBGAUDIO8 0xD8
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#define SETTINGS_REG_DBGAUDIO8_DEFAULT 0
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/* Playback samplerate */
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#define SETTINGS_REG_DBGAUDIO8_PLAYRATE_OFFS 0
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#define SETTINGS_REG_DBGAUDIO8_PLAYRATE_MASK 0xFFFFFFFFUL
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/* Audio debug register 9 */
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#define SETTINGS_REG_DBGAUDIO9 0xD9
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#define SETTINGS_REG_DBGAUDIO9_DEFAULT 0
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/* Playback volume (master and first channel) */
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#define SETTINGS_REG_DBGAUDIO9_PLAYVOL0_OFFS 0
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#define SETTINGS_REG_DBGAUDIO9_PLAYVOL0_MASK 0x0000FFFFUL
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#define SETTINGS_REG_DBGAUDIO9_PLAYVOL1_OFFS 16
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#define SETTINGS_REG_DBGAUDIO9_PLAYVOL1_MASK 0xFFFF0000UL
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/* Audio debug register 10 */
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#define SETTINGS_REG_DBGAUDIO10 0xDA
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#define SETTINGS_REG_DBGAUDIO10_DEFAULT 0
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/* Average playback buffer level */
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#define SETTINGS_REG_DBGAUDIO10_PLAYBUFAVG_OFFS 0
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#define SETTINGS_REG_DBGAUDIO10_PLAYBUFAVG_MASK 0x0000FFFFUL
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/* Audio debug register 11 */
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#define SETTINGS_REG_DBGAUDIO11 0xDB
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#define SETTINGS_REG_DBGAUDIO11_DEFAULT 0
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/* Minimum playback buffer level */
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#define SETTINGS_REG_DBGAUDIO11_PLAYBUFMIN_OFFS 0
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#define SETTINGS_REG_DBGAUDIO11_PLAYBUFMIN_MASK 0x0000FFFFUL
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/* Audio debug register 12 */
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#define SETTINGS_REG_DBGAUDIO12 0xDC
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#define SETTINGS_REG_DBGAUDIO12_DEFAULT 0
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/* Maximum playback buffer level */
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#define SETTINGS_REG_DBGAUDIO12_PLAYBUFMAX_OFFS 0
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#define SETTINGS_REG_DBGAUDIO12_PLAYBUFMAX_MASK 0x0000FFFFUL
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/* Audio debug register 13 */
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#define SETTINGS_REG_DBGAUDIO13 0xDD
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#define SETTINGS_REG_DBGAUDIO13_DEFAULT 0
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/* Average UAC2.0 Feedback Value since last playback */
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#define SETTINGS_REG_DBGAUDIO13_PLAYFBAVG_OFFS 0
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#define SETTINGS_REG_DBGAUDIO13_PLAYFBAVG_MASK 0xFFFFFFFFUL
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/* Audio debug register 14 */
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#define SETTINGS_REG_DBGAUDIO14 0xDE
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#define SETTINGS_REG_DBGAUDIO14_DEFAULT 0
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/* Minimum UAC2.0 Feedback Value since last playback */
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#define SETTINGS_REG_DBGAUDIO14_PLAYFBMIN_OFFS 0
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#define SETTINGS_REG_DBGAUDIO14_PLAYFBMIN_MASK 0xFFFFFFFFUL
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/* Audio debug register 15 */
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#define SETTINGS_REG_DBGAUDIO15 0xDF
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#define SETTINGS_REG_DBGAUDIO15_DEFAULT 0
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/* Maximum UAC2.0 Feedback Value since last playback */
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#define SETTINGS_REG_DBGAUDIO15_PLAYFBMAX_OFFS 0
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#define SETTINGS_REG_DBGAUDIO15_PLAYFBMAX_MASK 0xFFFFFFFFUL
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void Settings_Init();
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void Settings_Init();
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uint8_t Settings_RegWrite(uint8_t address, const uint8_t * buffer, uint8_t bufsize);
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uint8_t Settings_RegWrite(uint8_t address, const uint8_t * buffer, uint8_t bufsize);
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uint8_t Settings_RegRead(uint8_t address, uint8_t * buffer, uint8_t bufsize);
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uint8_t Settings_RegRead(uint8_t address, uint8_t * buffer, uint8_t bufsize);
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