2022-10-23 13:38:44 +00:00
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#include "usb_audio.h"
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2022-10-31 13:07:12 +00:00
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#include "stm32f3xx_hal.h"
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2022-11-03 16:19:31 +00:00
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#include "aioc.h"
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#include "tusb.h"
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2022-10-23 13:38:44 +00:00
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#ifndef AUDIO_SAMPLE_RATE
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#define AUDIO_SAMPLE_RATE 48000
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#endif
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2022-11-06 11:41:14 +00:00
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static bool mute[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
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static uint16_t volume[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX + 1]; // +1 for master channel 0
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static uint32_t sampFreq = AUDIO_SAMPLE_RATE;
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static uint8_t clkValid = 1;
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static audio_control_range_4_n_t(1) sampleFreqRng = {
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.wNumSubRanges = 1,
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.subrange[0] = {
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.bMin = AUDIO_SAMPLE_RATE,
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.bMax = AUDIO_SAMPLE_RATE,
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.bRes = 0
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}
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};
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2022-10-23 13:38:44 +00:00
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2022-11-03 17:57:12 +00:00
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#define FLAG_IN_START 0x00000010UL
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#define FLAG_OUT_START 0x00000100UL
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static volatile uint32_t flags;
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2022-10-23 13:38:44 +00:00
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//--------------------------------------------------------------------+
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// Application Callback API Implementations
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//--------------------------------------------------------------------+
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// Invoked when audio class specific set request received for an EP
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bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
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{
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(void) rhport;
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(void) pBuff;
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// We do not support any set range requests here, only current value requests
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TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
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// Page 91 in UAC2 specification
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uint8_t channelNum = TU_U16_LOW(p_request->wValue);
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uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
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uint8_t ep = TU_U16_LOW(p_request->wIndex);
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(void) channelNum; (void) ctrlSel; (void) ep;
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return false; // Yet not implemented
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}
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// Invoked when audio class specific set request received for an interface
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bool tud_audio_set_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
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{
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(void) rhport;
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(void) pBuff;
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// We do not support any set range requests here, only current value requests
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TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
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// Page 91 in UAC2 specification
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uint8_t channelNum = TU_U16_LOW(p_request->wValue);
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uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
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uint8_t itf = TU_U16_LOW(p_request->wIndex);
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(void) channelNum; (void) ctrlSel; (void) itf;
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return false; // Yet not implemented
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}
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// Invoked when audio class specific set request received for an entity
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bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff)
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{
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(void) rhport;
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// Page 91 in UAC2 specification
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uint8_t channelNum = TU_U16_LOW(p_request->wValue);
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uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
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uint8_t itf = TU_U16_LOW(p_request->wIndex);
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uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
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(void) itf;
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// We do not support any set range requests here, only current value requests
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TU_VERIFY(p_request->bRequest == AUDIO_CS_REQ_CUR);
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// If request is for our feature unit
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if ( entityID == 2 )
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{
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switch ( ctrlSel )
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{
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case AUDIO_FU_CTRL_MUTE:
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// Request uses format layout 1
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TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_1_t));
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mute[channelNum] = ((audio_control_cur_1_t*) pBuff)->bCur;
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TU_LOG2(" Set Mute: %d of channel: %u\r\n", mute[channelNum], channelNum);
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return true;
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case AUDIO_FU_CTRL_VOLUME:
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// Request uses format layout 2
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TU_VERIFY(p_request->wLength == sizeof(audio_control_cur_2_t));
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volume[channelNum] = (uint16_t) ((audio_control_cur_2_t*) pBuff)->bCur;
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TU_LOG2(" Set Volume: %d dB of channel: %u\r\n", volume[channelNum], channelNum);
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return true;
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// Unknown/Unsupported control
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default:
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TU_BREAKPOINT();
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return false;
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}
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}
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return false; // Yet not implemented
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}
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// Invoked when audio class specific get request received for an EP
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bool tud_audio_get_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request)
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{
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(void) rhport;
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// Page 91 in UAC2 specification
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uint8_t channelNum = TU_U16_LOW(p_request->wValue);
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uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
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uint8_t ep = TU_U16_LOW(p_request->wIndex);
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(void) channelNum; (void) ctrlSel; (void) ep;
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// return tud_control_xfer(rhport, p_request, &tmp, 1);
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return false; // Yet not implemented
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}
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// Invoked when audio class specific get request received for an interface
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bool tud_audio_get_req_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
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{
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(void) rhport;
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// Page 91 in UAC2 specification
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uint8_t channelNum = TU_U16_LOW(p_request->wValue);
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uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
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uint8_t itf = TU_U16_LOW(p_request->wIndex);
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(void) channelNum; (void) ctrlSel; (void) itf;
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return false; // Yet not implemented
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}
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// Invoked when audio class specific get request received for an entity
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bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * p_request)
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{
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(void) rhport;
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// Page 91 in UAC2 specification
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uint8_t channelNum = TU_U16_LOW(p_request->wValue);
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uint8_t ctrlSel = TU_U16_HIGH(p_request->wValue);
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// uint8_t itf = TU_U16_LOW(p_request->wIndex); // Since we have only one audio function implemented, we do not need the itf value
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uint8_t entityID = TU_U16_HIGH(p_request->wIndex);
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// Input terminal (Microphone input)
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2022-10-24 18:36:13 +00:00
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if (entityID == AUDIO_CTRL_ID_MIC_INPUT)
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2022-10-23 13:38:44 +00:00
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{
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switch ( ctrlSel )
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{
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case AUDIO_TE_CTRL_CONNECTOR:
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{
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// The terminal connector control only has a get request with only the CUR attribute.
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audio_desc_channel_cluster_t ret;
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// Those are dummy values for now
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ret.bNrChannels = 1;
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ret.bmChannelConfig = 0;
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ret.iChannelNames = 0;
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TU_LOG2(" Get terminal connector\r\n");
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return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
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}
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break;
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// Unknown/Unsupported control selector
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default:
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TU_BREAKPOINT();
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return false;
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}
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}
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// Feature unit
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2022-10-24 18:36:13 +00:00
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if (entityID == AUDIO_CTRL_ID_MIC_FUNIT)
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2022-10-23 13:38:44 +00:00
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{
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switch ( ctrlSel )
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{
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case AUDIO_FU_CTRL_MUTE:
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// Audio control mute cur parameter block consists of only one byte - we thus can send it right away
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// There does not exist a range parameter block for mute
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TU_LOG2(" Get Mute of channel: %u\r\n", channelNum);
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return tud_control_xfer(rhport, p_request, &mute[channelNum], 1);
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case AUDIO_FU_CTRL_VOLUME:
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switch ( p_request->bRequest )
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{
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case AUDIO_CS_REQ_CUR:
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TU_LOG2(" Get Volume of channel: %u\r\n", channelNum);
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return tud_control_xfer(rhport, p_request, &volume[channelNum], sizeof(volume[channelNum]));
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case AUDIO_CS_REQ_RANGE:
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TU_LOG2(" Get Volume range of channel: %u\r\n", channelNum);
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// Copy values - only for testing - better is version below
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audio_control_range_2_n_t(1)
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ret;
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ret.wNumSubRanges = 1;
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ret.subrange[0].bMin = -90; // -90 dB
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ret.subrange[0].bMax = 90; // +90 dB
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ret.subrange[0].bRes = 1; // 1 dB steps
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return tud_audio_buffer_and_schedule_control_xfer(rhport, p_request, (void*) &ret, sizeof(ret));
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// Unknown/Unsupported control
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default:
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TU_BREAKPOINT();
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return false;
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}
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break;
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// Unknown/Unsupported control
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default:
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TU_BREAKPOINT();
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return false;
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}
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}
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// Clock Source unit
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2022-10-24 18:36:13 +00:00
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if ( entityID == AUDIO_CTRL_ID_CLOCK )
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2022-10-23 13:38:44 +00:00
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{
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switch ( ctrlSel )
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{
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case AUDIO_CS_CTRL_SAM_FREQ:
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// channelNum is always zero in this case
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switch ( p_request->bRequest )
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{
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case AUDIO_CS_REQ_CUR:
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TU_LOG2(" Get Sample Freq.\r\n");
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return tud_control_xfer(rhport, p_request, &sampFreq, sizeof(sampFreq));
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case AUDIO_CS_REQ_RANGE:
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TU_LOG2(" Get Sample Freq. range\r\n");
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return tud_control_xfer(rhport, p_request, &sampleFreqRng, sizeof(sampleFreqRng));
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// Unknown/Unsupported control
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default:
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TU_BREAKPOINT();
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return false;
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}
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break;
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case AUDIO_CS_CTRL_CLK_VALID:
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// Only cur attribute exists for this request
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TU_LOG2(" Get Sample Freq. valid\r\n");
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return tud_control_xfer(rhport, p_request, &clkValid, sizeof(clkValid));
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// Unknown/Unsupported control
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default:
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TU_BREAKPOINT();
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return false;
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}
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}
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TU_LOG2(" Unsupported entity: %d\r\n", entityID);
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return false; // Yet not implemented
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}
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2022-11-03 17:57:12 +00:00
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bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t itf, uint8_t ep_in, uint8_t cur_alt_setting) {
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(void) rhport;
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(void) itf;
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(void) ep_in;
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(void) cur_alt_setting;
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2022-10-23 13:38:44 +00:00
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2022-11-03 17:57:12 +00:00
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if (flags & FLAG_IN_START) {
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/* Start ADC sampling as soon as device stacks starts loading data (will be a ZLP for first frame) */
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NVIC_EnableIRQ(ADC1_2_IRQn);
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flags &= (uint32_t) ~FLAG_IN_START;
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}
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2022-10-23 13:38:44 +00:00
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2022-11-03 17:57:12 +00:00
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return true;
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}
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2022-10-31 13:07:12 +00:00
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2022-11-03 17:57:12 +00:00
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bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting)
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2022-10-23 13:38:44 +00:00
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{
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2022-11-03 17:57:12 +00:00
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if (flags & FLAG_OUT_START) {
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uint16_t count = tud_audio_available();
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2022-10-23 13:38:44 +00:00
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2022-11-06 11:41:14 +00:00
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if (count >= (6 * CFG_TUD_AUDIO_EP_SZ_OUT)) {
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/* Wait until at least n frames are in buffer, then start DAC output */
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2022-11-03 17:57:12 +00:00
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flags &= (uint32_t) ~FLAG_OUT_START;
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NVIC_EnableIRQ(TIM3_IRQn);
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}
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}
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2022-10-23 13:38:44 +00:00
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2022-11-03 17:57:12 +00:00
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return true;
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2022-10-23 13:38:44 +00:00
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}
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2022-10-31 13:07:12 +00:00
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2022-11-06 11:41:14 +00:00
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2022-10-31 13:07:12 +00:00
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bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request)
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{
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(void) rhport;
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(void) p_request;
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2022-11-03 17:57:12 +00:00
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uint16_t itf = p_request->wIndex;
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uint16_t alt = p_request->wValue;
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switch(itf) {
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2022-11-03 16:19:31 +00:00
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case ITF_NUM_AUDIO_STREAMING_IN:
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2022-11-03 17:57:12 +00:00
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if (alt == 1) {
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/* Microphone channel has been activated */
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flags |= FLAG_IN_START;
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}
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2022-11-03 16:19:31 +00:00
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break;
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case ITF_NUM_AUDIO_STREAMING_OUT:
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2022-11-03 17:57:12 +00:00
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if (alt == 1) {
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/* Speaker channel has been activated */
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flags |= FLAG_OUT_START;
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}
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2022-11-03 16:19:31 +00:00
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break;
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default:
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TU_ASSERT(0, false);
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break;
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}
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|
2022-10-31 13:07:12 +00:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2022-11-03 17:57:12 +00:00
|
|
|
bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const *p_request) {
|
|
|
|
(void) rhport;
|
|
|
|
(void) p_request;
|
2022-10-23 13:38:44 +00:00
|
|
|
|
2022-11-03 17:57:12 +00:00
|
|
|
uint16_t itf = p_request->wIndex;
|
2022-11-03 16:19:31 +00:00
|
|
|
|
2022-11-03 17:57:12 +00:00
|
|
|
switch (itf) {
|
|
|
|
case ITF_NUM_AUDIO_STREAMING_IN:
|
|
|
|
/* Microphone channel has been stopped */
|
|
|
|
NVIC_DisableIRQ(ADC1_2_IRQn);
|
|
|
|
break;
|
2022-11-03 16:19:31 +00:00
|
|
|
|
2022-11-03 17:57:12 +00:00
|
|
|
case ITF_NUM_AUDIO_STREAMING_OUT:
|
|
|
|
/* Speaker channel has been stopped */
|
|
|
|
NVIC_DisableIRQ(TIM3_IRQn);
|
|
|
|
break;
|
2022-11-03 16:19:31 +00:00
|
|
|
|
2022-11-03 17:57:12 +00:00
|
|
|
default:
|
|
|
|
TU_ASSERT(0, false);
|
|
|
|
break;
|
|
|
|
}
|
2022-10-23 13:38:44 +00:00
|
|
|
|
2022-11-03 17:57:12 +00:00
|
|
|
return true;
|
2022-10-23 13:38:44 +00:00
|
|
|
}
|
|
|
|
|
2022-10-31 13:07:12 +00:00
|
|
|
void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t* feedback_param)
|
|
|
|
{
|
|
|
|
/* Configure parameters for feedback endpoint */
|
|
|
|
feedback_param->frequency.mclk_freq = 2 * HAL_RCC_GetPCLK1Freq();
|
|
|
|
feedback_param->sample_freq = AUDIO_SAMPLE_RATE;
|
2022-11-06 11:41:14 +00:00
|
|
|
feedback_param->method = AUDIO_FEEDBACK_METHOD_FREQUENCY_FIXED;
|
2022-10-31 13:07:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift)
|
|
|
|
{
|
|
|
|
static uint32_t prev_cycles = 0;
|
2022-11-06 11:41:14 +00:00
|
|
|
uint32_t this_cycles = TIM2->CCR1; /* Load from capture register, which is set in tu_stm32_sof_cb */
|
2022-10-31 13:07:12 +00:00
|
|
|
|
|
|
|
/* Calculate number of master clock cycles between now and last call */
|
2022-11-03 17:57:12 +00:00
|
|
|
uint32_t cycles = (uint32_t) (((uint64_t) this_cycles - prev_cycles) & 0xFFFFFFFFUL);
|
2022-11-06 11:41:14 +00:00
|
|
|
TU_ASSERT(cycles != 0, /**/);
|
2022-10-31 13:07:12 +00:00
|
|
|
|
|
|
|
/* Notify the USB audio feedback endpoint */
|
2022-11-06 11:41:14 +00:00
|
|
|
tud_audio_feedback_update(func_id, cycles);
|
2022-10-31 13:07:12 +00:00
|
|
|
|
|
|
|
/* Prepare for next time */
|
|
|
|
prev_cycles = this_cycles;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ADC1_2_IRQHandler (void)
|
|
|
|
{
|
|
|
|
if (ADC2->ISR & ADC_ISR_EOS) {
|
|
|
|
ADC2->ISR = ADC_ISR_EOS;
|
2022-11-06 11:41:14 +00:00
|
|
|
uint16_t value = ((int32_t) ADC2->DR - 32768) & 0xFFFFU;
|
|
|
|
tud_audio_write (&value, sizeof(value));
|
2022-10-31 13:07:12 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void TIM3_IRQHandler(void)
|
|
|
|
{
|
|
|
|
if (TIM3->SR & TIM_SR_UIF) {
|
|
|
|
TIM3->SR = (uint32_t) ~TIM_SR_UIF;
|
2022-11-03 17:57:12 +00:00
|
|
|
uint16_t items = tud_audio_available();
|
2022-10-31 13:07:12 +00:00
|
|
|
int16_t sample = 0x0000;
|
2022-11-03 17:57:12 +00:00
|
|
|
|
2022-10-31 13:07:12 +00:00
|
|
|
if (items > 0) {
|
|
|
|
tud_audio_read(&sample, sizeof(sample));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Load DAC holding register with sample */
|
2022-11-03 17:57:12 +00:00
|
|
|
DAC1->DHR12L1 = ((int32_t) sample + 32768) & 0xFFFFU;
|
2022-10-31 13:07:12 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void GPIO_Init(void)
|
|
|
|
{
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
|
|
|
|
|
|
GPIO_InitTypeDef ADCInGpio;
|
|
|
|
ADCInGpio.Pin = GPIO_PIN_2;
|
|
|
|
ADCInGpio.Mode = GPIO_MODE_ANALOG;
|
|
|
|
ADCInGpio.Pull = GPIO_NOPULL;
|
|
|
|
ADCInGpio.Speed = GPIO_SPEED_FREQ_LOW;
|
|
|
|
ADCInGpio.Alternate = 0;
|
|
|
|
HAL_GPIO_Init(GPIOB, &ADCInGpio);
|
|
|
|
|
|
|
|
GPIO_InitTypeDef SamplerateGpio;
|
|
|
|
SamplerateGpio.Pin = GPIO_PIN_0;
|
|
|
|
SamplerateGpio.Mode = GPIO_MODE_AF_PP;
|
|
|
|
SamplerateGpio.Pull = GPIO_NOPULL;
|
|
|
|
SamplerateGpio.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
|
|
SamplerateGpio.Alternate = GPIO_AF2_TIM3;
|
|
|
|
HAL_GPIO_Init(GPIOB, &SamplerateGpio);
|
|
|
|
|
|
|
|
GPIO_InitTypeDef DACOutGpio;
|
|
|
|
DACOutGpio.Pin = GPIO_PIN_4;
|
|
|
|
DACOutGpio.Mode = GPIO_MODE_ANALOG;
|
|
|
|
DACOutGpio.Pull = GPIO_NOPULL;
|
|
|
|
DACOutGpio.Speed = GPIO_SPEED_FREQ_LOW;
|
|
|
|
DACOutGpio.Alternate = 0;
|
|
|
|
HAL_GPIO_Init(GPIOA, &DACOutGpio);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void Timer_Init(void)
|
|
|
|
{
|
|
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
|
|
/* TODO: Use TIM6? */
|
|
|
|
/* TIM3_TRGO triggers ADC2 */
|
|
|
|
TIM3->CR1 = TIM_CLOCKDIVISION_DIV1 | TIM_COUNTERMODE_UP | TIM_AUTORELOAD_PRELOAD_ENABLE;
|
|
|
|
TIM3->CR2 = TIM_TRGO_UPDATE;
|
|
|
|
TIM3->PSC = 0;
|
|
|
|
TIM3->ARR = (2 * HAL_RCC_GetPCLK1Freq() / AUDIO_SAMPLE_RATE) - 1;
|
|
|
|
TIM3->EGR = TIM_EGR_UG;
|
|
|
|
#if 1 /* Output sample rate on compare channel 3 */
|
|
|
|
TIM3->CCMR2 = TIM_OCMODE_PWM1 | TIM_CCMR2_OC3PE;
|
|
|
|
TIM3->CCER = (0 << TIM_CCER_CC3P_Pos) | TIM_CCER_CC3E;
|
|
|
|
TIM3->CCR3 = 500;
|
|
|
|
#endif
|
|
|
|
TIM3->DIER = TIM_DIER_UIE;
|
|
|
|
TIM3->CR1 |= TIM_CR1_CEN;
|
|
|
|
|
2022-11-06 11:41:14 +00:00
|
|
|
NVIC_SetPriority(TIM3_IRQn, AIOC_IRQ_PRIO_AUDIO);
|
2022-10-31 13:07:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ADC_Init(void)
|
|
|
|
{
|
|
|
|
__HAL_RCC_ADC2_CLK_ENABLE();
|
|
|
|
|
|
|
|
ADC2->CR = 0x00 << ADC_CR_ADVREGEN_Pos;
|
|
|
|
ADC2->CR = 0x01 << ADC_CR_ADVREGEN_Pos;
|
|
|
|
|
|
|
|
for (uint32_t i=0; i<200; i++) {
|
|
|
|
asm volatile ("nop");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Select AHB clock */
|
|
|
|
ADC12_COMMON->CCR = (0x1 << ADC12_CCR_CKMODE_Pos) | (0x00 << ADC12_CCR_MULTI_Pos);
|
|
|
|
|
|
|
|
ADC2->CR |= ADC_CR_ADCAL;
|
|
|
|
|
|
|
|
while (ADC2->CR & ADC_CR_ADCAL)
|
|
|
|
;
|
|
|
|
|
|
|
|
ADC2->CR |= ADC_CR_ADEN;
|
|
|
|
|
|
|
|
/* Wait for ADC to be ready */
|
|
|
|
while (!(ADC2->ISR & ADC_ISR_ADRDY))
|
|
|
|
;
|
|
|
|
|
|
|
|
/* External Trigger on TIM3_TRGO, left aligned data with 12 bit resolution */
|
|
|
|
ADC2->CFGR = (0x01 << ADC_CFGR_EXTEN_Pos) | (0x04 << ADC_CFGR_EXTSEL_Pos) | (ADC_CFGR_ALIGN) | (0x00 << ADC_CFGR_RES_Pos);
|
|
|
|
|
|
|
|
/* Maximum sample time of 601.5 cycles for channel 12. */
|
|
|
|
ADC2->SMPR2 = 0x7 << ADC_SMPR2_SMP12_Pos;
|
|
|
|
|
|
|
|
/* Sample only channel 12 in a regular sequence */
|
|
|
|
ADC2->SQR1 = (12 << ADC_SQR1_SQ1_Pos) | (0 << ADC_SQR1_L_Pos);
|
|
|
|
|
|
|
|
/* Enable Interrupt Request */
|
|
|
|
ADC2->IER = ADC_IER_EOSIE;
|
|
|
|
|
|
|
|
/* Start ADC */
|
|
|
|
ADC2->CR |= ADC_CR_ADSTART;
|
|
|
|
|
2022-11-03 16:19:31 +00:00
|
|
|
NVIC_SetPriority(ADC1_2_IRQn, AIOC_IRQ_PRIO_AUDIO);
|
2022-10-31 13:07:12 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void DAC_Init(void)
|
|
|
|
{
|
|
|
|
__HAL_RCC_DAC1_CLK_ENABLE();
|
|
|
|
|
|
|
|
/* TSEL1 == TIM3 trigger */
|
|
|
|
__HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG);
|
|
|
|
|
|
|
|
DAC->CR = (0x1 << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1;
|
|
|
|
}
|
|
|
|
|
2022-10-23 13:38:44 +00:00
|
|
|
void USB_AudioInit(void)
|
|
|
|
{
|
2022-10-31 13:07:12 +00:00
|
|
|
GPIO_Init();
|
|
|
|
Timer_Init();
|
|
|
|
ADC_Init();
|
|
|
|
DAC_Init();
|
|
|
|
|
2022-10-23 13:38:44 +00:00
|
|
|
}
|